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1 typical a pplica t ion fea t ures descrip t ion 14v in , 4a step-down dc/dc module regulator the lt m ? 4624 is a complete 4a step-down switching mode module ? (micromodule) regulator in a tiny 6.25mm 6.25mm 5.01mm bga package. included in the package are the switching controller, power fets, inductor and sup - port components. operating over an input voltage range of 4v to 14v or 2.375v to 14v with an external bias supply, the l tm4624 supports an output voltage range of 0.6v to 5.5v, set by a single external resistor. its high efficiency design delivers 4a continuous, 5a peak, output current. only bulk input and output capacitors are needed. the ltm4624 supports selectable discontinuous mode operation and output voltage tracking for supply rail se - quencing. its high switching frequency and current mode control enable a ver y fast transient response to line and load changes without sacrificing stability . fault protection features include overvoltage, overcurrent and overtemperature protection. the ltm4624 is available with snpb (bga) or rohs compliant terminal finish. 4a, 1.5v output dc/dc module step-down regulator 12v in efficiency vs load current a pplica t ions n complete solution in <1cm 2 (single-sided pcb) or 0.5cm 2 (dual-sided pcb) n wide input voltage range: 4v to 14v n input voltage down to 2.375v with external bias n 0.6v to 5.5v output voltage n 4a dc, 5a peak output current n 2% total dc output voltage error n current mode control, fast transient response n output voltage tracking n selectable discontinuous mode n power good indicator n overvoltage, overcurrent and overtemperature protection n 6.25mm 6.25mm 5.01mm bga package n telecom, datacom, networking and industrial equipment n medical diagnostic equipment n data storage rack units and cards n test and debug systems l , lt, ltc, ltm, module, linear technology and the linear logo are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 40.2k 4624 ta01a 10f 16v v in 4v to 14v v out 1.5v 4a 47f 6.3v 0.1f v in sv in run intv cc mode track/ss freq v out fb pgood comp gnd sgnd ltm4624 load current (a) 0 efficiency (%) 80 85 90 4 4624 ta01b 75 70 50 1 2 3 55 60 65 100 95 v out = 5v v out = 3.3v v out = 2.5v v out = 1.5v v out = 1.2v v out = 1v click to view associated techclip videos. ltm4624 4624fc for more information www.linear.com/ltm4624
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , sv in .................................................... C0 .3v to 15v v out (note 4) ................................... C 0.3v to sv in or 6v run .......................................................... C 0.3v to sv in intv cc ...................................................... C0 .3v to 3.6v pgood, mode, track/ss, freq ........ C 0.3v to intv cc comp, fb (note 4) ................................ C0 .3v to intv cc internal operating junction temperature range (notes 2, 5) ............................................ C 40c to 125c storage temperature range .................. C 55c to 125c peak solder reflow body temperature ................. 245 c (note 1) (see pin functions, pin configuration table) bga package 25-lead (6.25mm 6.25mm 5.01mm) top view nc sv in v in v out intv cc mode gnd a 5 1 2 3 4 sgnd freq nc track/ss run b c d e nc pgood fb comp t jmax = 125c, v jctop = 17c/w, v jcbottom = 11c/w, v jb + v ba = 22c/w, v ja = 22c/w, v ja derived from 95mm w 76mm pcb with 4 layers v values determined per jesd51-12, weight = 0.5g e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = sv in = 12v per the typical application shown on the front page. o r d er i n f or m a t ion symbol parameter conditions min typ max units switching regulator section: per channel v in input dc voltage sv in = v in l 4 14 v v out(range) output voltage range l 0.6 5.5 v v out(dc) output voltage, total variation with line and load c in = 22f, c out = 100f ceramic, r fb = 40.2k, mode = intv cc ,v in = 4v to 14v, i out = 0a to 4a (note 3) 0c to 125c C40c to 125c l 1.477 1.47 1.50 1.50 1.523 1.53 v v v run run pin on threshold v run rising 1.1 1.2 1.3 v i q(svin) input supply bias current v in = 12v, v out = 1.5v, mode = intv cc v in = 12v, v out = 1.5v, mode = gnd shutdown, run = 0, v in = 12v 6 2 11 ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 4a 0.62 a i out(dc) output continuous current range v in = 12v, v out = 1.5v 0 4 a part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4624ey#pbf sac305 (rohs) ltm4624y e1 bga 3 C40c to 125c ltm4624iy#pbf sac305 (rohs) ltm4624y e1 bga 3 C40c to 125c ltm4624iy snpb (63/37) ltm4624y e0 bga 3 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www .linear.com/packaging ltm4624 4624fc for more information www.linear.com/ltm4624
3 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4624 is tested under pulsed load conditions such that t j t a . the ltm4624e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4624i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. symbol parameter conditions min typ max units v out (line)/v out line regulation accuracy v out = 1.5v, v in = 4v to 14v, i out = 0a l 0.04 0.15 %/v v out (load)/v out load regulation accuracy v out = 1.5v, i out = 0a to 4a l 1 1.5 % v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, v in = 12v, v out = 1.5v 5 mv v out(start) turn-on overshoot i out = 0a, c out = 100f ceramic, v in = 12v, v out = 1.5v 30 mv t start turn-on time c out = 100f ceramic, no load, track/ss = 0.01f, v in = 12v, v out = 1.5v 2.5 ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 160 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 40 s i outpk output current limit v in = 12v, v out = 1.5v 5 7 a v fb voltage at fb pin i out = 0a, v out = 1.5v i out = 0a, v out = 1.5v, C40c to 125c l 0.594 0.591 0.60 0.60 0.606 0.609 v v i fb current at fb pin (note 4) 30 na r fbhi resistor between v out and fb pins 60.05 60.40 60.75 k i track/ss track pin soft-start pull-up current track/ss = 0v 2.5 4 a v in(uvlo) v in undervoltage lockout v in falling v in hysteresis 2.4 2.6 350 2.8 v mv t on(min) minimum on-time (note 4) 40 ns t off(min) minimum off-time (note 4) 70 ns v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C13 7 C10 10 C7 13 % % i pgood pgood leakage 2 a v pgl pgood voltage low i pgood = 1ma 0.02 0.1 v v intvcc internal v cc voltage sv in = 4v to 14v 3.2 3.3 3.4 v v intvcc load reg intv cc load regulation i cc = 0ma to 20ma 0.5 % f osc oscillator frequency 1 mhz note 3: see output current derating curves for different v in , v out and t a . note 4: 100% tested at wafer level. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. the l denotes the specifications which apply over the full internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = sv in = 12v per the typical application shown on the front page. ltm4624 4624fc for more information www.linear.com/ltm4624
4 typical p er f or m ance c harac t eris t ics 1v output transient response 3.3v output transient response 1.5v output transient response 5v output transient response 2.5v output transient response efficiency vs load current with 5v in efficiency vs load current with 12v in dcm mode efficiency, v out = 1.5v load current (a) 0 efficiency (%) 80 85 90 4 4624 g01 75 70 50 1 2 3 55 60 65 100 95 v out = 3.3v v out = 2.5v v out = 1.5v v out = 1.2v v out = 1v load current (a) 0 efficiency (%) 80 85 90 4 4624 g02 75 70 50 1 2 3 55 60 65 100 95 v out = 5v v out = 3.3v v out = 2.5v v out = 1.5v v out = 1.2v v out = 1v load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 4624 g03 0 0.01 v in = 5v v in = 12v v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1v i out = 3a to 4a, 1a/s output capacitor = 1 47f ceramic 20s/div 4624 g04 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.5v i out = 3a to 4a, 1a/s output capacitor = 1 47f ceramic 20s/div 4624 g05 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 2.5v i out = 3a to 4a, 1a/s output capacitor = 1 47f ceramic 20s/div 4624 g06 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 3.3v i out = 3a to 4a, 1a/s output capacitor = 1 47f ceramic 20s/div 4624 g07 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 5v i out = 3a to 4a, 1a/s output capacitor = 1 47f ceramic 20s/div 4624 g08 ltm4624 4624fc for more information www.linear.com/ltm4624
5 start-up with no load short-circuit with no load start-up with 4a load short-circuit with 4a load output ripple recovery to no load from short circuit start into pre-bias output 12v input to 1.8v output, 50% load transient response 5v input to 1.2v output, 50% load transient response typical p er f or m ance c harac t eris t ics i in 0.1a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 150f sanyo electrolytic capacitor (optional) + 22f ceramic capacitor output capacitor = 47f ceramic capacitor soft-start capacitor = 0.1f 5ms/div 4624 g09 i in 0.2a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 150f sanyo electrolytic capacitor (optional) + 22f ceramic capacitor output capacitor = 47f ceramic capacitor soft-start capacitor = 0.1f 5ms/div 4624 g10 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 150f sanyo electrolytic capacitor (optional) + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 20s/div 4624 g11 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 150f sanyo electrolytic capacitor (optional) + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 20s/div 4624 g12 i out 20a/div v out 200mv/div v in = 12v v out = 1v input capacitor = 22f sanyo electrolytic capacitor (optional) + 2 22f ceramic capacitor output capacitor = 2 47f ceramic capacitor soft-start capacitor = 0.1f 5s/div 4624 g13 5mv/div ac-coupled v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor (optional) + 2 22f ceramic capacitor output capacitor = 2 47f ceramic capacitor soft-start capacitor = 0.1f 500s/div 4624 g14 v in 2v/div v out 1v/div v in = 12v v out = 5v input capacitor = 22f sanyo electrolytic capacitor (optional) + 2 22f ceramic capacitor output capacitor = 2 47f ceramic capacitor soft-start capacitor = 0.1f 1s/div 4624 g15 v out 100mv/div ac-coupled load step 2a/div v in = 12v v out = 1.8v i out = 2a to 4a, 1a/s output capacitor = 1 47f ceramic 50s/div 4624 g16 v out 50mv/div ac-coupled load step 1a/div v in = 5v v out = 1.2v i out = 2a to 4a, 1a/s output capacitor = 1 47f ceramic 50s/div 4624 g17 ltm4624 4624fc for more information www.linear.com/ltm4624
6 p in func t ions comp (a1): current control threshold and error amplifier compensation point. the current comparators trip thresh - old is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v . t ie the comp pins together for parallel operation. the device is internally compensated. track/ss (a2): output tracking and soft-start input. allows the user to control the rise time of the output volt - age. putting a voltage below 0.6v on this pin bypasses the internal reference input to the error amplifier , and ser vos the fb pin to match the track/ss voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifier. theres an internal 2.5a pull-up current from intv cc on this pin, so putting a capacitor here provides a soft-start function. run (a3): run control input of the switching mode regulator. enables chip operation by tying run above 1.25v. pulling it below 1.1v shuts down the part. do not leave floating. freq (a4): frequency is set internally to 1mhz. an ex - ternal resistor can be placed from this pin to sgnd to increase frequency , or from this pin to int v cc to reduce frequency. see the applications information section for frequency adjustment. nc (a5, b2, b5): no connect pins. pins are not connected internally. float or ground these pins. fb (b1): the negative input of the error amplifier. internally, this pin is connected to v out with a 60.4k precision resis - tor. different output voltages can be programmed with an additional resistor between the fb and sgnd pins. tying the fb pins together allows for parallel operation. see the applications information section for details. gnd (b3, c3, d3-d4, e3): power ground pins for both input and output returns. sgnd (b4): signal ground connection. tie to gnd with minimum distance. connect freq resistor, comp com - ponent, mode, track/ss component, fb resistor to this pin as needed. v out (c1, d1-d2, e1-e2): power output pins. apply out - put load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. pgood (c2): output power good with open-drain logic. pgood is pulled to ground when the voltage on the fb pin is not within 10% of the internal 0.6v reference. mode (c4): operation mode select. tie this pin to intv cc to force continuous synchronous operation at all output loads. tying it to sgnd enables discontinuous mode operation at light loads. do not leave floating. sv in (c5): signal v in . filtered input voltage to the on-chip 3.3v regulator. tie this pin to the v in pin in most applica- tions. connect sv in to an external voltage supply of at least 4v which must also be greater than v out . v in (d5, e5): power input pins. apply input voltage be- tween these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. intv cc (e4): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. this pin is internally decoupled to gnd with a 1f low esr ceramic capacitor. package row and column labeling may vary among module products. review each package layout carefully. ltm4624 4624fc for more information www.linear.com/ltm4624
7 b lock diagra m decoupling r equire m en t s symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4v to 14v, v out = 1.5v) i out = 4a 4.7 10 f c out external output capacitor requirement (v in = 4v to 14v, v out = 1.5v) i out = 4a 22 47 f figure 1. simplified ltm4624 block diagram power control fb 60.4k 1f 0.1f r fb 40.2k 0.22f c in 10f intv cc v out mode track/ss run comp 1f v out v in sv in 10k pgood v out 1.5v 4a v in 4v to 14v intv cc gnd 1h 4624 bd freq 162k internal comp sgnd internal filter c out 47f ltm4624 4624fc for more information www.linear.com/ltm4624
8 o pera t ion the ltm4624 is a standalone nonisolated switch mode dc/dc power supply. it can deliver up to 4a dc (5a peak) output current with few external input and output capacitors. this module provides precisely regulated output voltage adjustable between 0.6v to 5.5v via one external resistor over a 4v to 14v input voltage range. with an external bias supply, this module operates with an input voltage down to 2.375v. the typical application schematic is shown in figure 20. the ltm4624 contains an integrated constant on-time valley current mode regulator, power mosfets, inductor, and other supporting discrete components. the default switching frequency is 1mhz. for noise-sensitive applica - tions, the switching frequency can be adjusted by external resistors. see the applications information section. with current mode control and internal feedback loop compensation, the l tm4624 module has sufficient stabil - ity margins and good transient per formance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast cur - rent limiting. foldback current limiting is provided in an over current condition indicated by a drop in v fb reducing inductor valley current to approximately 40% of the origi - nal value. internal output overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. continuous operation is forced during ov and uv conditions except during start-up when the track pin is ramping up to 0.6v pulling the run pin below 1.1v forces the controller into its shutdown state, turning off both power mosfets and most of the internal control circuitry. at light load currents, discontinuous mode (dcm) operation can be enabled to achieve higher efficiency compared to continu - ous mode (ccm) by pulling the mode pin to sgnd. the track/ss pin is used for power supply tracking and soft-start programming. see the applications informa- tion section. ltm4624 4624fc for more information www.linear.com/ltm4624
9 a pplica t ions i n f or m a t ion the typical ltm4624 application circuit is shown in figure? 20. external component selection is primarily determined by the input voltage, the output voltage and the maximum load current. refer to table 6 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratios that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of the regulator . the minimum off-time limit imposes a maximum duty cycle which can be calculated as: d max = 1 C (t off(min) ? f sw ) where t off(min) is the minimum off-time, typically 70ns for ltm4624, and f sw (hz) is the switching frequency. conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as: d min = t on(min) ? f sw where t on(min) is the minimum on-time, typically 40ns for ltm4624. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. note that additional thermal derating may be applied. see the thermal considerations and output current derating section in this data sheet. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor connects the v out and fb pins together. adding a resistor, r fb , from fb pin to sgnd programs the output voltage: r fb = 0.6v v out C 0.6v ? 60.4k table 1. r fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 r fb (k) open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 input decoulping capacitors the ltm4624 module should be connected to a low ac impedance dc source. for the regulator, a 10f input ceramic capacitor is required for rms ripple current de - coupling. bulk input capacitance is only needed when the input sour ce impedance is compromised by long inductive leads, traces or not enough sour ce capacitance. the bulk capacitor can be an aluminum electrolytic capacitor or polymer capacitor. without considering the inductor ripple current, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1Cd ( ) where % is the estimated efficiency of the power module. output decoulping capacitors with an optimized high frequency, high bandwidth design, only a single low esr output ceramic capacitor is required for the ltm4624 to achieve low output ripple voltage and very good transient response. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 6 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 1a and 2a load-step transient. the linear technology ltpowercad? design tool is available to download online for output ripple, stability and transient response analysis for further optimization. ltm4624 4624fc for more information www.linear.com/ltm4624
10 a pplica t ions i n f or m a t ion discontinuous current mode (dcm) in applications where low output ripple and high efficiency at intermediate current are desired, discontinuous current mode (dcm) should be used by connecting the mode pin to sgnd. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. forced continuous current mode (ccm) in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to intv cc . in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4624s output voltage is in regulation. operating frequency the operating frequency of the ltm4624 is optimized to achieve the compact package size and the minimum out- put ripple voltage while still keeping high efficiency. the default operating frequency is internally set to 1mhz. in most applications, no additional frequency adjusting is required. if any operating frequency other than 1mhz is required by application, the operating frequency can be increased by adding a resistor, r fset , between the freq pin and sgnd, as shown in figure 21. the operating frequency can be calculated as: f hz ( ) = 1.6e11 162k||r fset ? ( ) the operating frequency can also be decreased by adding a resistor between the freq pin and intv cc , calculated as: f hz ( ) = 1mhz C 2.8e11 r fset ? ( ) the programmable operating frequency range is from 800khz to 4mhz. soft-start and output voltage tracking the track/ss pin provides a means to either soft start the regulator or track it to a different power supply. a ca - pacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 2.5a current sour ce will charge up the external soft-start capacitor towards int v cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 2.5a where c ss is the capacitance on the track/ss pin. cur- rent foldback and forced continuous mode are disabled during the soft-start process. ltm4624 4624fc for more information www.linear.com/ltm4624
11 a pplica t ions i n f or m a t ion output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure 2 and figure?3 show an example waveform and schematic of ratiometric tracking where the slave regulators output slew rate is proportional to the masters. since the slave regulators track/ss is connected to the masters output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6v, the slave time slave output master output output voltage 4624 f02 figure 2. output ratiometric tracking waveform freq v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd r fb(ma) 40.2k ltm4624 10f 16v v in 4v to 15v v out(ma) 1.5v 4a 47f 6.3v r tr(bot) 40.2k r fb(sl) 60.4k r tr(top) 60.4k freq v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd 4624 f03 ltm4624 10f 16v v out(sl) 1.2v 4a 47f 6.3v figure 3. example schematic of ratiometric output voltage tracking ltm4624 4624fc for more information www.linear.com/ltm4624
12 a pplica t ions i n f or m a t ion output voltage and the master output voltage should satisfy the following equation during start-up: v out(sl) ? r fb(sl) r fb(sl) + 60.4k = v out(ma) ? r tr(bot) r tr(top) + r tr(bot) the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure 3. following the previous equation, the ratio of the masters output slew rate (mr) to the slaves output slew rate (sr) is determined by: mr sr = r fb(sl) r fb(sl) + 60.4k r tr(bot) r tr(top) + r tr(bot) for example, v out(ma) =1.5v, mr = 1.5v/1ms and v out(sl) = 1.2v, sr = 1.2v/1ms as shown in figure 5. from the equa - tion, we could solve that r tr(top) = 60.4k and r tr(bot) = 40.2k are a good combination for the ratiometric tracking. the track/ss pin will have the 2.5a current source on when a resistive divider is used to implement tracking on the slave regulator. this will impose an offset on the track/ss pin input. smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track/ss pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking in which the masters output slew rate (mr) is the same as the slaves output slew rate (sr), waveform as shown in figure 4. figure 4. output coincident tracking waveform time master output slave output output voltage 4624 f04 from the equation, we could easily find that, in coincident tracking, the slave regulators track/ss pin resistor divider is always the same as its feedback divider: r fb(sl) r fb(sl) + 60.4k = r tr(bot) r tr(top) + r tr(bot) for example, r tr(top) = 60.4k and r tr(bot) = 60.4k is a good combination for coincident tracking for a v out(ma) = 1.5v and v out(sl) = 1.2v application. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin is pulled low when the output voltage exceeds a 10% window around the regulation point. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltm4624s pgood falling edge includes a blanking delay of approximately 52 switching cycles. stability compensation the ltm4624s internal compensation loop is designed and optimized for use with low esr ceramic output capacitors. table 5 is provided for most application requirements. in case a bulk output capacitor is required for output ripple or dynamic transient spike reduction, an additional 10pf to 15pf feedforward capacitor (c ff ) is needed between the v out and fb pins. the ltpowercad design tool is available for control loop optimization. ltm4624 4624fc for more information www.linear.com/ltm4624
13 a pplica t ions i n f or m a t ion run enable pulling the run pin to ground forces the ltm4624 into its shutdown state, turning off both power mosfets and most of its internal control circuitry. bringing the run pin above 0.7v turns on the internal reference only, while still keeping the power mosfets off. increasing the run pin voltage above 1.25v will turn on the entire chip. pre-biased output start-up there may be situations that require the power supply to start up with some charge on the output capacitors. the ltm4624 can safely power up into a pre-biased output without discharging it. the ltm4624 accomplishes this by forcing discontinuous mode (dcm) operation until the track/ss pin voltage reaches 0.6v reference voltage. this will prevent the bg from turning on during the pre-biased output start-up which would discharge the output. do not pre-bias ltm4624 with an output voltage above intv cc voltage (3.3v) or set voltage by fb resistor which - ever is lower. overtemperature protection the internal overtemperature protection monitors the junc - tion temperature of the module. if the junction temperature re ac hes approximately 160c, both power switches will be turned off until the temperature drops about 15c cooler. low input application the ltm4624 module has a separate sv in pin which makes it suitable for low input voltage applications down to 2.375v. the sv in pin is the single input of the whole control circuitry while the v in pin is the power input which directly connects to the drain of the top mosfet. in most applications where v in is greater than 4v, connect sv in directly to v in with a short trace. an optional filter, con - sisting of a resistor (1 to 10) between sv in and v in along with a 0.1f bypass capacitor between sv in and ground, can be placed for additional noise immunity. this filter is not necessary in most cases if good pcb layout practices are followed (see figure 19). in a low input voltage (2.375v to 4v) application, or to reduce power dissipation by the internal bias ldo, connect sv in to an external voltage higher than 4v with a 0.1f local bypass capacitor. figure 21 shows an example of a low input voltage application. please note the sv in voltage cannot go below the v out voltage. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd 51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in jesd 51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulators thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are, in and of themselves, not relevant to providing guidance of thermal per formance; instead, the derating cur ves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51-12; these coefficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. ltm4624 4624fc for more information www.linear.com/ltm4624
14 a pplica t ions i n f or m a t ion 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages, but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure 5; blue resistances are contained within the module regulator , whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4624 be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laborator y testing in a controlled environment chamber to reasonably define and correlate the thermal resistance figure 5. graphical representation of jesd 51-12 thermal coefficients 4624 f05 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance ltm4624 4624fc for more information www.linear.com/ltm4624
15 a pplica t ions i n f or m a t ion values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4624 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jsed 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4624 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due diligence yields the set of derating curves shown in this data sheet. after these laboratory tests have been performed and correlated to the ltm4624 model, then the jb and ba are summed together to provide a value that should closely equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. the 1.0v, 1.5v, 3.3v and 5v power loss curves in figures?6 to 9 can be used in coordination with the load current derating curves in figures 10 to 16 for calculating an approximate ja thermal resistance for the ltm4624 with various airflow conditions. the power loss curves are taken at room temperature, and are increased with a multiplicative factor according to the ambient tempera - ture. this approximate factor is: 1.4 for 120c at junction temperature. maximum load current is achievable while increasing ambient temperature as long as the junction temperature is less than 120c, which is a 5c guard band from maximum junction temperature of 125c. when the ambient temperature reaches a point where the junction temperature is 120c, then the load current is lowered to maintain the junction at 120c while increasing ambient temperature up to 120c. the derating curves are plotted with the output current starting at 4a and the ambient tem - perature at 30c. the output voltages are 1.0v, 1.5v, 3.3v and 5v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example, in figure?11 the load current is derated to ~3a at ~95c with no air flow or heat sink and the power loss for the 12v to 1.0v at 3a output is about 1.15w. the 1.15w loss is calculated with the ~0.82w room temperature loss from the 12v to 1.0v power loss curve at 3a, and the 1.4 multiplying factor at 120c junction temperature. if the 95c ambient temperature is subtracted from the 120c junction temperature, then the difference of 25c divided by 1.15w equals a 22c/w ja thermal resistance. table ?2 specifies a 22c/w value which is very close. table 3, table?4 and table 5 provide equivalent thermal resistances for 1.5v 3.3v and 5v outputs with and without airflow and heat sinking. the derived thermal resistances in table 3, table?4 and table 5 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multiplicative factors. the printed circuit board is a 1.6mm thick 4-layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimen - sions are 95mm 76mm. ltm4624 4624fc for more information www.linear.com/ltm4624
16 figure 6. 1.0v loss figure 7. 1.5v loss figure 8. 3.3v loss a pplica t ions i n f or m a t ion figure 9. 5v loss figure 12. 5v to 1.5v derating curve, no heat sink figure 10. 5v to 1v derating curve, no heat sink figure 11. 12v to 1v derating curve, no heat sink load current (a) 0 1.0 1.2 1.4 4 4624 f06 0.8 0.6 1 2 3 5 0.4 0.2 0 power loss (w) v in = 12v v in = 5v load current (a) 0 power loss (w) 0.6 0.8 1.0 3 5 4642 f07 0.4 0.2 0 1 2 4 1.2 1.4 1.6 v in = 12v v in = 5v load current (a) 0 power loss (w) 0.6 0.8 1.0 3 5 4642 f07 0.4 0.2 0 1 2 4 1.2 1.4 1.6 v in = 12v v in = 5v load current (a) 0 power loss (w) 1.5 2.0 2.5 4 4642 f09 1.0 0.5 0 1 2 3 5 v in = 12v ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 120 4.5 4642 f10 1.0 40 50 60 70 80 130 3.0 3.5 4.0 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f11 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f12 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ltm4624 4624fc for more information www.linear.com/ltm4624
17 a pplica t ions i n f or m a t ion figure 15. 12v to 3.3v derating curve, no heat sink figure 16. 12v to 5v derating curve, no heat sink figure 13. 12v to 1.5v derating curve, no heat sink figure 14. 5v to 3.3v derating curve, no heat sink ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f13 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f14 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f15 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 0.5 1.5 2.0 2.5 90 100 110 4.5 4642 f16 1.0 40 50 60 70 80 120 3.0 3.5 4.0 400lfm 200lfm 0lfm ltm4624 4624fc for more information www.linear.com/ltm4624
18 table 2. 1.0v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 10, 11 5, 12 figure 6 0 none 22 figures 10, 11 5, 12 figure 6 200 none 19 figures 10, 11 5, 12 figure 6 400 none 18 table 3. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 12, 13 5, 12 figure 7 0 none 22 figures 12, 13 5, 12 figure 7 200 none 19 figures 12, 13 5, 12 figure 7 400 none 18 table 4. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figures 14, 15 5, 12 figure 8 0 none 22 figures 14, 15 5, 12 figure 8 200 none 19 figures 14, 15 5, 12 figure 8 400 none 18 table 5. 5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja(c/w) figure 16 12 figure 9 0 none 22 figure 16 12 figure 9 200 none 19 figure 16 12 figure 9 400 none 18 ltm4624 4624fc for more information www.linear.com/ltm4624
19 a pplica t ions i n f or m a t ion table 6. output voltage response vs component matrix (refer to figure 20) c in part number value c out1 part number value c out2 part number value murata grm21br61c106ke15l 10f, 16v, 0805, x5r murata grm21br60j476me15 47f, 6.3v, 0805, x5r sanyo 4tpe100mzb 4v 100f taiyo yuden emk212bj106kg-t 10f, 16v, 0805, x5r taiyo yuden jmk212bj476mg-t 47f, 6.3v, 0805, x5r murata grm31cr61c226me15l 22f, 16v, 1206, x5r taiyo yuden emk316bj226ml-t 22f, 16v, 1206, x5r v out (v) c in (ceramic) (f) c in (bulk) c out1 (ceramic) (f) c out2 (bulk) (f) c ff (pf) v in (v) droop (mv) p-p derivation (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) 1 10 47 5, 12 5 72 40 1 1 90.9 1 10 100 10 5, 12 5 60 40 1 1 90.9 1 10 47 5, 12 5 127 40 2 1 90.9 1 10 100 10 5, 12 5 90 40 2 1 90.9 1.2 10 47 5, 12 5 76 40 1 1 60.4 1.2 10 100 10 5, 12 5 65 40 1 1 60.4 1.2 10 47 5, 12 5 145 40 2 1 60.4 1.2 10 100 10 5, 12 5 103 40 2 1 60.4 1.5 10 47 5, 12 5 80 40 1 1 40.2 1.5 10 100 10 5, 12 5 70 40 1 1 40.2 1.5 10 47 5, 12 5 161 40 2 1 40.2 1.5 10 100 10 5, 12 5 115 40 2 1 40.2 1.8 10 47 5, 12 5 95 40 1 1 30.1 1.8 10 100 10 5, 12 5 80 40 1 1 30.1 1.8 10 47 5, 12 5 177 40 2 1 30.1 1.8 10 100 10 5, 12 5 128 40 2 1 30.1 2.5 10 47 5, 12 5 125 40 1 1 19.1 2.5 10 100 10 5, 12 5 100 50 1 1 19.1 2.5 10 47 5, 12 5 225 40 2 1 19.1 2.5 10 100 10 5, 12 5 161 50 2 1 19.1 3.3 10 47 5, 12 5 155 40 1 1 13.3 3.3 10 100 10 5, 12 5 122 60 1 1 13.3 3.3 10 47 5, 12 5 285 40 2 1 13.3 3.3 10 100 10 5, 12 5 198 60 2 1 13.3 5 10 47 5, 12 5 220 40 1 1 8.25 5 10 47 5, 12 5 420 40 2 1 8.25 ltm4624 4624fc for more information www.linear.com/ltm4624
20 a pplica t ions i n f or m a t ion figure 19. recommended pcb layout v in c out v out 4624 f19 gnd c in r fb safety considerations the ltm4624 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and over current protection. layout checklist/example the high integration of ltm4624 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessar y . ? use large pcb copper areas for high current paths, including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? bring out test points on the signal pins for monitoring. figure 19 gives a good example of the recommended layout. ltm4624 4624fc for more information www.linear.com/ltm4624
21 a pplica t ions i n f or m a t ion figure 20. 4v in to 14v in , 1.5v output at 4a design figure 21. 2.375v in to 5v in , 1v output with 2mhz operating frequency v in sv in run intv cc mode track/ss pgood ltm4624 freq v out 10f 16v 47f 6.3v v in 4v to 14v v out 1.5v 4a fb comp gnd 40.2k sgnd 4624 f20 0.1f v in sv in run intv cc mode track/ss pgood ltm4624 freq 162k 5v v out 10f 16v 1f 6.3v 47f 6.3v v in 2.375v to 5v v out 1v 4a fb comp gnd 90.9k sgnd 4624 f21 0.1f ltm4624 4624fc for more information www.linear.com/ltm4624
22 figure 22. 4v in to 14v in , 1.2v and 1.5v with coincident tracking a pplica t ions i n f or m a t ion v in sv in run intv cc mode track/ss pgood ltm4624 freq v out 10f 16v 2 47f 6.3v 47f 6.3v 60.4k v in 4v to 14v v out 1.5v 4a v out2 1.2v 4a fb 40.2k comp gnd 60.4k 60.4k 4624 f22 sgnd 0.1f v in sv in run intv cc mode track/ss pgood ltm4624 freq v out fb comp gnd sgnd ltm4624 4624fc for more information www.linear.com/ltm4624
23 p ackage descrip t ion ltm4624 component bga pinout pin id function pin id function pin id function pin id function pin id function a1 comp a2 track/ss a3 run a4 freq a5 nc b1 fb b2 nc b3 gnd b4 sgnd b5 nc c1 v out c2 pgood c3 gnd c4 mode c5 sv in d1 v out d2 v out d3 gnd d4 gnd d5 v in e1 v out e2 v out e3 gnd e4 intv cc e5 v in package row and column labeling may vary among module products. review each package layout carefully. ltm4624 4624fc for more information www.linear.com/ltm4624
24 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 0.630 0.025 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 12345 pin 1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature ?b (25 places) a detail b package side view z m x yzddd m zeee a2 d e e b f g detail a 0.3175 0.3175 bga 25 0913 rev b ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? bga package 25-lead (6.25mm 6.25mm 5.01mm) (reference ltc dwg # 05-08-1905 rev b) detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 6.25 6.25 1.27 5.08 5.08 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 25 // bbb z z h2 h1 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes ltm4624 4624fc for more information www.linear.com/ltm4624
25 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 8/13 update freq pin description update output overvoltage protection description 6 8 b 2/14 add snpb bga package option update run threshold 1, 2 2 c 7/14 add techclip video hyperlink update absolute maximum ratings section update pre-biased output start-up section 1 2 13 ltm4624 4624fc for more information www.linear.com/ltm4624
26 ? linear technology corporation 2013 lt 0714 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm4624 r ela t e d p ar t s p ackage p ho t o part number description comments ltm4619 dual 26v, 4a step-down module regulator 4.5v v in 26.5v, 0.8v v out 5v, pll input, v out tracking, pgood, 15mm 15mm 2.82mm lga ltm4618 26v, 6a step-down module regulator 4.5v v in 26.5v, 0.8v v out 5v, pll input, v out tracking, 9mm 15mm 4.32mm lga l tm4628 dual 26v , 8a step-down module regulator 4.5v v in 26.5v, 0.6v v out 5.5v, remote sense amplifier, internal temperature sensing output, 15mm 15mm 4.32mm lga ltm4614 dual 5v, 4a module regulator 2.375v v in 5.5v, 0.8v v out 5v, 15mm 15mm 2.82mm lga ltm4608a 5v, 8a step-down module regulator with tracking, margining and frequency synchronization 2.7v v in 5.5v, 0.6v v out 5v, pll input, clock output, v out tracking and margining, pgood, 9mm 15mm 2.82mm lga ltm4616 dual 5v, 8a step-down module regulator with tracking, margining and frequency synchronization 2.7v v in 5.5v, 0.6v v out 5v, pll input, clock output, v out tracking and margining, pgood, 15mm 15mm 2.82mm lga ltm8045 inverting or sepic module dc/dc converter with up to 700ma output current 2.8v v in 18v, 2.5v v out 15v, synchronizable, no derating or logic- level shift for control inputs when inverting, 6.25mm 11.25mm 4.92mm bga lt c ? 2978 octal digital power supply manager with eeprom i 2 c/pmbus interface, configuration eeprom, fault logging, 16-bit adc with 0.25% tue, 3.3v to 15v operation ltc2974 quad digital power supply manager with eeprom i 2 c/pmbus interface, configuration eeprom, fault logging, per channel voltage, current and temperature measurements design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. ltm4624 4624fc for more information www.linear.com/ltm4624

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